1. Field of the Invention
The present invention relates to a digital/analog converter being capable of outputting an analog amount of currents corresponding to a digital amount of an input signal.
2. Description of the Related Art
A digital/analog converter (hereinafter referred simply to as a xe2x80x9cD/A converterxe2x80x9d) has many transistors adapted to output an amount of reference currents precisely set in advance. However, depending on a place where each transistor is located on a board, a minute departure from a reference current amount occurs in an amount of currents output from each transistor. This phenomenon is attributable to changes in conditions of biases to be fed to each transistor due to a voltage drop caused by a minute resistance possessed by a ground line itself, variations in processing conditions imposed during manufacturing, or a like. As a result, a difference occurs in an amount of output currents among transistors. This difference depends on relative positional relations among transistors. For example, if transistors are placed in proximity to one another, they are placed under similar conditions and therefore such the difference in an amount of output currents does not occur easily among the transistors. However, if transistors are placed apart from one another, such the difference readily occurs among the transistors. In order to achieve a D/A converter having an output characteristic being excellent in linearity by avoiding occurrence of such the phenomenon, various technological developments are proceeding (for example, refer to Patent Reference No. 1).
Outlines of the above Patent Reference No.1 are described by referring to attached drawings. FIG. 4 is a circuit diagram showing configurations of a conventional D/A converter. FIG. 5 is a graph showing an amount of changes in a current output caused by a difference in mounting locations of transistors.
As shown in FIG. 4, the conventional D/A converter includes an output terminal 101 to output an amount of currents corresponding to a digital amount of an input current, a switch controlling section 102 to exert switching control according to a predetermined number of bits (here in the example, 2 bits), a current converting section 103 to produce an amount of currents corresponding to a digital amount of an input current, an output switch 104 to be ON-OFF controlled by the switch controlling section 102, and a bias terminal 130 to which a bias voltage to be fed to each transistor is applied.
The current converting section 103 has four current controlling blocks P1 to P4 each being made up of four MOS (Metal Oxide Semiconductor) transistors. Now let it be assumed that a predetermined output current amount being a reference current amount for each of the MOS transistors T11 to T44 is I0. Mounting locations of the current controlling blocks P1 to P4 in the graph shown in FIG. 5 correspond to a mounting location (left to right facing the drawing) of each block on a board. Also, let it be assumed that, as shown in FIG. 5, a difference between an output current amount and a reference current amount I0 for each of transistors in the current controlling block P1 is xe2x88x922xcex94 I0, a difference between an output current amount and a reference current amount I0 for each of transistors in the current controlling block P2 is xe2x88x92xcex94 I0, a difference between an output current amount and a reference current amount I0 for each of transistors in the current controlling block P3 is xcex94 I0, a difference between an output current amount and a reference current amount I0 for each of transistors in the current controlling block P4 is 2xcex94 I0.
In this case, a current amount Is1, flowing through a switch SW1 is a composite sum of a current amount flowing through the transistor T14 being I0xe2x88x922xcex94 I0, a current amount flowing through the transistor T21 being I0xe2x88x92xcex94 I0, a current amount flowing through the transistor T34 being I0+xcex94 I0 and a current amount flowing through the transistor T41 being I0+2xcex94 I0, that is, Is1=4I0.
Similarly, a current amount IS2 flowing through a switch SW2 is a composite sum of a current amount flowing through the transistor T13 being I0xe2x88x922xcex94 I0, a current amount flowing through the transistor T22 being I0xe2x88x92xcex94 I0, and a current amount flowing through the transistor T33 being I0+xcex94 I0, and a current amount flowing through the transistor T42 being I0+2xcex94 I0, that is, IS2=4I0. Likewise, a current amount flowing through a switch SW3 being IS3=4I0 and a current amount flowing through a switch SW4 being IS4=4I0 
That is, each of the current amounts Is1, IS2, IS3, and IS4 flowing respectively through each of the switch SW1 to SW4, since a variation in an amount of currents relative to the reference current amount I0 is a sum total of current amounts of four transistors to be used for comparison, becomes equal to one another. This enables avoidance of variations in current amounts occurring due to a difference in mounting locations of each transistor among the current controlling blocks P1 to P4 on the board.
As a prior art technological reference related to the present invention, a following reference is available:
Patent Reference No.1: Japanese Patent Application Laid-open No. Hei 4-262622 (Summary)
However, the conventional D/A converter disclosed in the Japanese Patent Application Laid-open No. Hei 4-262622 has problems to be solved. That is, though the conventional D/A converter having 2-bit resolution is disclosed in the above Patent Application, if a D/A converter having, for example, 4-bit resolution has to be achieved based on the technology disclosed in the above Patent Application, it is made necessary for the D/A converter to be configured so that 15 pieces of current controlling blocks each having 15 pieces of transistors are controlled by 15 pieces of switches, which causes extremely increased occupied areas of the D/A converter on a board. To solve this problem, a method may be available in which resolution is enhanced by weighting low-order 2 bits, out of the 4 bits, for controlling, thereby inhibiting the increase in the occupied area of the block. In this case, in addition to block groups, which correspond to high-order 2 bits, configured in a manner similar to the above-mentioned conventional technology, 2 blocks through each of which an amount of currents being xc2xc and xc2xd times an amount of currents flowing the above block groups flows are independently provided on which weighting is exerted for controlling.
In this case, though a difference in current amounts which occurs due to a difference in mounting locations in block groups configured in a manner similar to the above conventional technology can be cancelled by configuring as above, since each of the blocks for weight controlling is independently provided, it is difficult to reduce variations in an amount of currents. Therefore, such the method described above has not yet become commercially practical.
In view of the above, it is an object of the present invention to provide a D/A converter which is capable of inhibiting an increase in occupied areas of the D/A converter on a board and of obtaining an output characteristic being excellent in linearity.
According to a first aspect of the present invention, there is provided a D /A converter including:
first current controlling device groups, each group being partitioned by a predetermined number of current controlling devices and each outputting a current to define an amount of currents corresponding to a bit value of an input digital signal;
second current controlling device groups, each group being partitioned by a predetermined number of current controlling devices being cascaded a specified current controlling device in the first current controlling device groups and each producing a composite sum of currents output from the specified current controlling device corresponding to cascaded connection;
an output switch outputting a composite current summed by the second current controlling device group based on switch control corresponding to a bit value of an input digital signal; and
wherein a current to be fed to the output switch is divided at a specified ratio by at least one of the second current controlling groups.
In the foregoing, a preferable mode is one wherein each of current controlling devices included in the first current controlling device groups and the second current controlling device groups is located in a manner so as to unify bias conditions on each current controlling device included in each of the current controlling device groups.
Also, a preferable mode is one wherein a number of the second current controlling device groups is equal to that of the first current controlling device.
Also, a preferable mode is one wherein each of the first current controlling groups includes a bias controlling device to exert control on a bias voltage to be supplied to each of the current controlling devices in the first current controlling groups using a current having a specified value.
Also, a preferable mode is one wherein each of the bias controlling devices makes up a current mirror circuit together with other current controlling devices contained in each of the first current controlling device groups.
Furthermore, a preferable mode is one wherein each of the current controlling devices contained in the first current controlling device groups and the second current controlling device groups is a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor).